Analog-to-digital (A/D) converters are electrical circuit devices that convert continuous signals, such as voltages or currents, from the analog domain to the digital domain where the signals are represented by numbers. A variety of A/D converter types exist, including flash A/Ds, sub-ranging A/Ds, successive approximation A/Ds, and integrating A/Ds. Another type is known as a sigma delta or delta sigma (e.g., Δ-Σ) A/D converter that includes a sigma delta modulator operating as a type of noise shaping encoder, typically with a 1–3 bit quantized digital output. Delta sigma (e.g., Δ-Σ) or sigma delta modulators are often used in mixed signal integrated A/D converters, because of their insensitivity to CMOS process linearity and matching problems when compared to other A/D converter types. These features make Δ-Σ based mixed signal solutions very attractive for a number of applications, such as audio, receiver channels of communication devices (wireless in particular), sensor interface circuits and measurement systems.
Delta sigma converters are operated at a significantly higher sampling rate than the bandwidth of the analog input signal, a technique referred to as oversampling, wherein the analog input signal is sampled at a very high sampling rate in order to perform a noise shaping function. The oversampling is commonly performed at a multiple of the Nyquist rate (FN) for a given input signal frequency content (e.g., sampling frequency FS is often 10 to 1000 times FN), wherein quantization noise power is spread over a bandwidth equal to the sampling frequency. Noise shaping filters, typically integrators, are commonly provided in the forward signal path of the delta sigma modulator. Digital filtering is performed on the oversampled digital output to achieve a high resolution, and decimation is employed to reduce the effective sampling rate back to the “Nyquist” rate.
A conventional second order delta sigma modulator 2 is illustrated in FIG. 1, comprising first and second analog adder/integrators 4 and 6, respectively. The first adder/integrator 4 comprises a first summing junction 12 and a first integrator (e.g., low pass filter) 16, and the second adder/integrator 6 comprises a second summing junction 18 and an integrator filter 22. The first summing junction 12 receives an analog input signal VIN via an input gain stage 14i and a first feedback signal FB1 via a feedback gain stage 14f from a first digital-to-analog converter (DAC or D/A) 112d. The modulator 2 may be a continuous time modulator or the input signal VIN may be periodically sampled via a switching element 8. An error signal (e.g., the difference between the input and feedback signals according to the relative gains 14i and 14f) is provided to the input of the first integrator 16, which provides an integrator output through a second input gain stage 20i to the second summing junction 18. The summing junction 18 also receives a second feedback signal FB2 via a second feedback gain stage 20f from a second DAC 26b. The second summing junction 18 provides an error signal (e.g., the difference between the integrator output signal from the first integrator 16 and the second feedback signal FB2) to the input of the second integrator filter 22.
The modulator 2 further comprises an analog-to-digital (A/D) converter or quantizer 24 receiving the output signal from the second integrator 22. The A/D converter 24 generates an n-bit quantized or digital output signal D1 . . . . Dn, where n is a positive integer. The DAC converters 26a and 26b provide the analog feedback signals FB1 and FB2, respectively, in accordance with the digital output D1 . . . Dn of the A/D converter 24. A digital decimation filter 28 reduces undesirable noise in the quantized digital output signal D1 . . . . Dn. The digital filter 28 acts as an anti-aliasing filter with respect to the final sampling rate and filters out higher frequency noise produced by the noise shaping process of the modulator 2. Final data reduction is performed by digitally resampling the filtered output at a lower rate using a process called decimation in the filter 28, wherein decimation removes redundant signal information introduced by the oversampling process.
According to one popular design approach, switched capacitor circuits may be used in constructing the delta sigma converter 2, for example, in the adder/integrators 4 and 6, the A/D 24, and/or the DACs 26, to facilitate integration in CMOS mixed signal fabrication processes. For instance, in the converter 2, the adder/integrators 4 and 6 are individually fabricated using an integrator amplifier (e.g., operational amplifier) and a switched capacitor circuit. The switched capacitor circuits may provide for relative gain adjustments of input signal levels by using different capacitor values and/or by grouping of series or parallel-coupled capacitors of like value, wherein the gain adjustments are shown in FIG. 1 as gain stages 14, and 20 in the first and second adder/integrators 4 and 6, respectively. Also, the DAC converters 26 may individually comprise a group of capacitors of ideally identical capacitance values, for instance, wherein the analog feedback signals FB1 and FB2 are provided by selectively coupling certain ones of the capacitors to certain reference voltages according to the quantized signal D1 . . . Dn. Similarly, the A/D converter 24 may be constructed using switched capacitor circuits.
In many modern applications, such as wireless communications products, low power consumption and low voltage operation are important design considerations for analog-to-digital converters. In the conventional converter 2, the amplifiers inside the integrators 16 and 22 are the major source of current consumption. Furthermore, amplifier nonlinearity becomes more problematic as supply voltage levels are decreased. For a flash type A/D quantizer 24, if the number of levels required is relatively small, for example, 3 or 4 bits (e.g., 8 to 10 levels), the number of comparators and the corresponding power consumption can be reduced. Also, the non-linearity of the DAC converters 26 can be mitigated through dynamic element matching (DEM) techniques. Hence, the effect of DAC imperfections on the quantization noise shaping can be reduced for low voltage operation. However, the ability to significantly reduce power consumption without degrading device performance is limited. While eliminating one stage of the converter 2 may result in lower power consumption, the noise shaping performance would go from second order to first order, whereby the device performance would be worsened. Accordingly, it is desirable to reduce the power consumption of analog-to-digital converter systems, while providing adequate noise shaping.